1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a flash memory device capable of performing high speed read and write operations.
2. Description of the Related Art
In general, a flash memory having eXecution In Place (XIP) functionality may be used for a portable device, for example, that requires memory having a small size or a short boot time. The XIP functionality enables programs to be executed directly from the flash memory. Codes stored in an XIP flash memory may be executed within the flash memory without first having to transfer the execute codes into random access memory (RAM). The XIP functionality enables the same execution of many application programs, while reducing the required RAM capacity.
Historically, typical NAND flash memories were not able to provide XIP functionality, so NOR flash memories were used as XIP memories. Recently, though, NAND flash memories capable of supporting XIP functionality have been developed. NAND flash memories may be desirable over NOR flash memories as XIP memories due to their low cost and high density.
A metal strapping technique has been used to reduce resistance of a signal line, e.g., formed of polysilicon, having a relatively large resistance. A signal line formed by the metal strapping technique may reduce the resistance using a metal conductor and a contact formed on the signal line, improving a signal transfer speed of the semiconductor device. A reduction in signal line resistance may enable a corresponding reduction in power. Also, a signal line (e.g., a common source line) formed by the metal strapping technique reduces coupling effect to increase operating reliability.
FIG. 1 is a circuit diagram showing a structure of a conventional XIP flash memory. Referring to FIG. 1, the XIP flash memory includes memory cell units 10, 20, 30 and 40, each of which has two selection transistors ST<n> and GT<n> and one cell transistor MC<n>. For convenience of description, the cell structure of the XIP flash memory will be described referring to only one memory cell unit, the memory cell unit 10, as an example.
The selection transistors ST<0> and GT<0> of the memory cell unit 10 respectively correspond to the string selection transistor SST and the ground selection transistor GST of a typical NAND flash memory. However, the memory cell unit 10 of the XIP flash memory may include only one cell transistor MC<0>, where a typical NAND flash memory may include multiple cell transistors connected in series between the string selection transistor and the ground selection transistor. The memory cell unit 10 is supplied with selection signals through the selection signal lines SSL<0> and GSL<0> and with a word line voltage through a word line WL<0>. The lines SSL<0>, WL<0> and GSL<0> are selectively connected to the memory cell unit 10 via high voltage switches PG<0>, PG<1> and PG<2>, respectively, which are switched on under the control of an X-decoder (not shown).
As illustrated in FIG. 1, three high-voltage switches are used to transfer control signals to each of the memory cell units 10, 20, 30 and 40. Also, the memory cell units 10 and 20 share a bit line BL<0> and a common source line CSL, and the memory cell units 30 and 40 share a bit line BL<1> and the common source line CSL.
FIG. 2 is a diagram showing a cross-section taken along a dashed line A-A′ in FIG. 1. FIG. 2 shows a schematic cross-section of the memory cells when a metal strapping technique is applied to word lines in an XIP flash memory. Referring to FIG. 2, in general, the control gates of selection transistors ST<0>, ST<2>, GT<0> and GT<2> are respectively connected to corresponding metal strapping lines MS1, MS3, MS5 and MS7 via contacts, and the control gates of the cell transistors MC<0> and MC<2> are respectively connected to corresponding metal strapping lines MS2 and MS6 via contacts. A common source line CSL formed on a diffusion layer in a P-type substrate is connected to a metal strapping line MS4.
In this configuration, seven metal strapping lines MS1 to MS7 are required for two memory cell units sharing the common source line and a bit line. The metal strapping lines of the XIP flash memory increase the chip size. Also, although the metal strapping lines have lower resistance than polysilicon lines, it is difficult to form the metal strapping lines and to reduce their corresponding line widths. Accordingly, increases in operation reliability and speed of an XIP flash memory is accompanied by increased cost.